Minimum qualifications: Bachelor's degree in Computer Science, Electrical Engineering, a related field, or equivalent practical experience. 3 years of experience with industry-standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips. Experience with SystemVerilog (i.e. SystemVerilog Assertions or functional coverage). Preferred qualifications: Master's degree or PhD in Electrical Engineering. 6 years of work experience with full verification life cycle. Experience verifying digital logic at RTL using SystemVerilog for ASICs. Experience in Power aware verification, Gate level simulations, and Post silicon bring-up. Strong problem solver, communicator and team player. About the job
Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As a TPU ASIC Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
The US base salary range for this full-time position is $127,000-$187,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google . Responsibilities Plan the verification of complex digital design blocks, understand the design specification, and interact with design engineers to identify important verification scenarios. Create a constrained-random verification environment using SystemVerilog and Universal Verification Methodology (UVM). Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out.
