This position is in a cutting-edge implementation product, in next generation synthesis and P&R tools.
The candidate will be required to work on building and enhancing the next generation flow for performance, power, area (PPA) and runtime. This will involve identifying the opportunity for improving PPA, proposing a good solution, implementing it, thoroughly testing it, and supporting it post-deployment.
What You'll Do:
Working on latest implementation technologies (Synthesis , Multi Source CTS , Floorplanning etc ) to solve complex PPA challenges. Working on developing and deploying synthesis and PNR methodologies for advanced nodes by collaborating with key stake holders. Providing technical solutions by identifying design and/or EDA tool issues and provide appropriate solution effectively and translate the findings into requirements for R&D to improve both tool behavior as adaptive long-term solutions. Develop project-specific design flows to improve PPA. Closely interacting with Synopsys R&D team and product development team to develop future technologies RTL to GDSII and understanding possible impacts of a technology challenge through the flow. Experience in independently debugging and resolving Synth & PnR implementation challenges. Candidate must have good exposure towards methodology changes to achieve targeted PPA metrics for complex designs. You will contribute to all phases of physical design of complex blocks, sub-systems from RTL to delivery of final GDSII.
Perform hands-on physical design implementation using Synopsys tools (DC, ICC2, FC) and physical verification tasks (ICV) in advanced process nodes of 5NM, 3NM, 2NM.
Physical design tasks include Synthesis, floor-planning, place and route, CTS, timing closure, IR/EM analysis, and Formality for block level and subsystem-level flat and hierarchical designs. Physical verification tasks include creating ICV setup and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debugging, and implementing fixes in the physical design database.
What You'll Need:
Minimum 5 Years with a B.Tech and an experience in SoC Physical Design Skills – hands-on working experience with PnR, STA and PV tools. Delivering timing clean blocks/chip level flow methodologies that meet design targets. Education – B. Tech /M. Tech in Electronics Engineering. The individual must be self-motivated and dedicated with strong debug skills. Requires proficiency in scripting (tcl / unix / perl) Excellent communication skills including ability to interface with customers and business unit personnel are essential.
Job Requirements
1. At least 5 years of work experience in RTL synthesis and PNR flows.
2. Strong Scripting skills: TCL, Perl and Python
3. Strong debugging skills for Placement, CTS, Power, Timing closure and DRC convergence.
4. Strong analytical and problem-solving skills.
5. Good understanding of chip design flow.
6. Must be a team player, clear in written and oral communication skills and open to work with diverse teams across multiple time zones.
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